Flexfet™

A Better Kind of CMOS

Flexfet is an advanced CMOS process characterized by an Independently Double Gated transistor. The novel design of the Flexfet transistor brings many benefits not realized in standard CMOS processes.

Flexfet provides Dynamic Threshold Control (DTC), enabling Vt to be controlled on-the-fly while the IC is in operation. With DTC, designers are not locked into choosing a Vt process corner. DTC allows the same IC to be optimized for speed and power, adjusted as the system operation requires.

Flexfet delivers Ultra Low Power (ULP) operation, running at as little as 0.5V, fully depleted, at speeds that is orders of magnitude faster than sub-threshold approaches to low power. Flexfet ULP enables systems to maximize power savings without sacraficing speed.

Flexfet is inherently radiation tolerant. The unique independently double gated design and SOI processing of Flexfet delivers a process that is both SEE and TID hard, making Flexfet extremely useful in avionics and space systems.

Flexfet enables integrated sensors such as photodiodes to be built on the same die as the CMOS, delivering monolithic detectors. In the example of photodetectors, the photodiode is fabricated in the handle silicon and the ROIC CMOS is fabricated on the SOI layer. This delivers a Monolithic Active Pixel Sensor (MAPS) for backside illuminated sensors.

Flexfet is a gate-last process, which enables integration of novel materials with low thermal budgets.

Flexfet is commercially available as a foundry process from American Semiconductor with standard Process Development Kits available for 180nm and 130nm nodes, and the Radiation Effects Process Development Kit (RE-PDK) developed with support from Air Force Research Labs SHARE program.

Flexfet ULP was developed with support from Air Force Research Labs. The video below is a demonstration of Flexfet Ultra Low Power operation.

Flexfet Diagram

Flexfet Status

• Flexfet 180nm CMOS

  • Pre-production process
  • Currently released for prototype and engineering product builds
  • Preliminary Design Package (PDP) and Process Development Kit (PDK) available
  • Technology Readiness Level (TRL) 6
    • Transistor and parametric testing completed at wafer and package levels
    • Flexfet 180nm is a good candidate to support advanced IC experiments at TRL1 to TRL6
  • Multilayer metal options available
  • Copper BEOL available
  • Integrated detector options available

• Flexfet 130nm CMOS

  • Pre-production process
  • Preliminary Design Package (PDP) available
  • Technology Readiness Level (TRL) 5
    • Flexfet 130nm offered for research programs at TRL1 to TRL5
  • Multilayer metal options available
  • Copper BEOL available

Flexfet is Advanced CMOS Technology that enables cutting edge designs

Logic

• Dynamic Threshold Control (DTC) for on-the-fly optimization of power and performance
• Ultra Low Power (ULP) voltage ranges available down to 0.5V without using subthreshold design
• DTC for active compensation of extreme temperature, supply voltage, process variation, and dose accumulation effects

Imagers / Detectors

• Supports integration of Flexfet CMOS with detector diodes in the substrate
• JFET bottom gate shields the Flexfet CMOS from the effects of voltages applied to the substrate

Memory

• Non-volatile memory integrating new dielectrics via Flexfet gate-last process

Analog / Mixed Signal

• Opportunities for lowering analog and mixed signal voltages
• Utilize Flexfet transistor isolation, low noise, low power, and Dynamic Threshold Control